For the semiconductor industry, optical photolithography has been the major technique and continues to be the engine that powers Moore's Law, which states, roughly, the number of transistors per integrated circuit chip doubles every two year. Recently, hyper-numerical aperture (NA) immersion 193 nm lithography has replaced 157 nm for 32 nm groundrule technology and pushed enhanced-ultraviolet (EUV) photolithography further to 22 nm groundrule technology. Many resolution enhancement technology (RET) methods have also contributed to the extension of optical photolithography to print very low k1 images. The value of k1 can be found using the optical projection lithography resolution equation W=k1λ/NA, where W is the minimum printable feature size, λ is the exposure wavelength (e.g. 193 nm, 157 nm), NA is the numerical aperture of the lithography system and k1 is a lithographic constant of the system.
Currently, double exposure (DE) has emerged to a method to reduce k1 in the fabrication of integrated circuit chips. Several double exposure schemes have been developed. A first DE scheme is called is double dipole lithography (DDL). In DDL X-axis critical images placed on a first mask and Y-axis critical images are placed on a second photomask. A layer of photoresist is exposed through the first mask with an X dipole and then the layer of photoresist is exposed through the second mask using a Y dipole. A second DE scheme is double exposure double etch (DE2). In DE2, a first layer of photoresist is exposed through a first mask and images etched into a substrate (or an underlying layer). The first photoresist layer is then removed. A second layer of photoresist is exposed through a second mask and images etched into the substrate (or the underlying layer). The second photoresist layer is then removed.
Both these techniques however, suffer from distortions introduced into the photoresist patterns. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.